豪威(Omnivision)筆試題目
面試筆試3.08W
Omnivision examiner use only
2005 china career fair exam
1 logic design
e is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no big the fifoshould be in order to avoid data over/under_run?please select theminimum depth below to meet the requirement.
A.160 b.200 c.800 d .1000
osedly there is acombinational circuit between two registersdriven by a will you do if the delay of the combinationalcircuit is greater than the clock signal?
reduce clock frequency increase clock frequency
make it pipelining d to make it multi_cycle
h of the follow circuits can generate gitch free gated_clk?
ys@(posedge clk) gated <=en;assign gated_clk=gated&~clk;
ys@(negedge clk) gated <=en;assign gated_clk=gated&~clk;
ys@(posedge clk) gated <=en;assign gated_clk=gated|~clk;
ys@(negedge clk) gated <=en;assign gated_clk=gated|~clk;
’re working on a specification of a system with some parameter has min,typ and max h columnwould you put setup and hold time?
p time in max,hold time in min
p time in min,hold time in max
in max
in min
e are 3 ants at 3corners of a triangle. They randomly startmoving towards another is the probability that won’tcollide?
a.0
b.1/8
c/1/4
d.1/3
you look at a clock and the time is 3: is angle between the hour and the minute hand?
a.0
b.360/48
3.360/12
d.360/4
many times per day a clock’s hands overlap?
a.11
b.22
c.24
d.26
8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q= is the max clock frequency the circuit can handle?
A.200mhz
b.250mhz
c.500mhz
d.1ghz
ical design
re tape-out,which routine check should be performed for your layout database in 0.18 um process?
&antenna
lation
to fix antenna effect?
the wire wider and shorter
ge lower metal to upper metal
ect with diode of metal and diffusion
ge upper metal to lower metal
e.b&c
se expain lvs
c versus schematic
ut versus schematic
ut via synthesis
c via synthesis
to control clock skew?
balanced clock tree
ease the fanout
clock buffer evenly
ease clock latency
to avoid hold_time violation?
r the clock speed
clock arrive later
clock arrive earlier
data arrive later
data arrive earlier
kinds of factors reflect good floor plan?
routing
timing met
gh power supply
d.a&b
e.a&b&c
cause cell delay?
t-pin transition time
ut-pin capacitance.
ut-pin resistance
d.a&b
e.b&c
need i/o pads for each chip?
protection
age level shift
h-up prevention
d.a&c
e.a&b&c
h one is worse-case in 0.18um process?
1.1.8v,25c
2.1.98v,125c
3.1.62v,-40c
4.1.62v,125c
5.1.98v,-40c
power plan is not good,what’ll happen to the chip?
a.hot-spot
age drop
ng not met
ing is tough
of above
itecture design
are two images,the first image has a person in front of ablackboard in a classroom and the second image has a person in front ofa lush two images are compressed using the jpeg algorithm.
first image will have larger file size.
second image will have a larger file size.
would you round a 10b number,x,at the 3rd(上角)bit?
a.(x>>2)<<2.
b.(x>>3)<<3.
c.((x+4)>>2)<<2
d.((x+4)>>2)<<3
e.((x+8)>>2)<<3
f.((x+8)>>3)<<3
happens if the number in 2 is negative?
A ignore
it absolute ,do the operation in 2,and add sign back
of the above
would you multiply a 4 in hardware?
4 adders each is offset from the provious adder by 1bit.
a booth multip;ier with 4b coefficient.
wires.
a barrel shifter.
is a fifo?what is a filo?which one is a queue? Which one is a stack?
is a queue and filo is a stack.
is the name of a dog. Filo is the name of a cat.
is a stack and filo is a queue.
would you design a barrel shifter?
multiple stages of 2乘2 multiplexers
a crossbar switch that can switch any inputs to any outputs
a clos network
muxes to switch between all combinations of hardwired shifts.
還有chip verification、algorithm design、hardware design、analog design。
2005 china career fair exam
1 logic design
e is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no big the fifoshould be in order to avoid data over/under_run?please select theminimum depth below to meet the requirement.
A.160 b.200 c.800 d .1000
osedly there is acombinational circuit between two registersdriven by a will you do if the delay of the combinationalcircuit is greater than the clock signal?
reduce clock frequency increase clock frequency
make it pipelining d to make it multi_cycle
h of the follow circuits can generate gitch free gated_clk?
ys@(posedge clk) gated <=en;assign gated_clk=gated&~clk;
ys@(negedge clk) gated <=en;assign gated_clk=gated&~clk;
ys@(posedge clk) gated <=en;assign gated_clk=gated|~clk;
ys@(negedge clk) gated <=en;assign gated_clk=gated|~clk;
’re working on a specification of a system with some parameter has min,typ and max h columnwould you put setup and hold time?
p time in max,hold time in min
p time in min,hold time in max
in max
in min
e are 3 ants at 3corners of a triangle. They randomly startmoving towards another is the probability that won’tcollide?
a.0
b.1/8
c/1/4
d.1/3
you look at a clock and the time is 3: is angle between the hour and the minute hand?
a.0
b.360/48
3.360/12
d.360/4
many times per day a clock’s hands overlap?
a.11
b.22
c.24
d.26
8.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q= is the max clock frequency the circuit can handle?
A.200mhz
b.250mhz
c.500mhz
d.1ghz
ical design
re tape-out,which routine check should be performed for your layout database in 0.18 um process?
&antenna
lation
to fix antenna effect?
the wire wider and shorter
ge lower metal to upper metal
ect with diode of metal and diffusion
ge upper metal to lower metal
e.b&c
se expain lvs
c versus schematic
ut versus schematic
ut via synthesis
c via synthesis
to control clock skew?
balanced clock tree
ease the fanout
clock buffer evenly
ease clock latency
to avoid hold_time violation?
r the clock speed
clock arrive later
clock arrive earlier
data arrive later
data arrive earlier
kinds of factors reflect good floor plan?
routing
timing met
gh power supply
d.a&b
e.a&b&c
cause cell delay?
t-pin transition time
ut-pin capacitance.
ut-pin resistance
d.a&b
e.b&c
need i/o pads for each chip?
protection
age level shift
h-up prevention
d.a&c
e.a&b&c
h one is worse-case in 0.18um process?
1.1.8v,25c
2.1.98v,125c
3.1.62v,-40c
4.1.62v,125c
5.1.98v,-40c
power plan is not good,what’ll happen to the chip?
a.hot-spot
age drop
ng not met
ing is tough
of above
itecture design
are two images,the first image has a person in front of ablackboard in a classroom and the second image has a person in front ofa lush two images are compressed using the jpeg algorithm.
first image will have larger file size.
second image will have a larger file size.
would you round a 10b number,x,at the 3rd(上角)bit?
a.(x>>2)<<2.
b.(x>>3)<<3.
c.((x+4)>>2)<<2
d.((x+4)>>2)<<3
e.((x+8)>>2)<<3
f.((x+8)>>3)<<3
happens if the number in 2 is negative?
A ignore
it absolute ,do the operation in 2,and add sign back
of the above
would you multiply a 4 in hardware?
4 adders each is offset from the provious adder by 1bit.
a booth multip;ier with 4b coefficient.
wires.
a barrel shifter.
is a fifo?what is a filo?which one is a queue? Which one is a stack?
is a queue and filo is a stack.
is the name of a dog. Filo is the name of a cat.
is a stack and filo is a queue.
would you design a barrel shifter?
multiple stages of 2乘2 multiplexers
a crossbar switch that can switch any inputs to any outputs
a clos network
muxes to switch between all combinations of hardwired shifts.
還有chip verification、algorithm design、hardware design、analog design。
-
強生(中國)筆試題
這是強生(中國)2004年筆試題的第一部分知識域的部分考題。馬斯洛的需要層次理論?人口抽樣的統計方法?ISO的全稱?三角形中一個!的交通標誌表示什麼意思?APEC的全稱?電子現金的好處?軟盤有病毒怎麼處理?新技術革命的標誌?產品生命週期的問題?我國要在2010年將人口控制在?花...
-
AMD北京筆試經歷
分軟件,硬件兩套卷子,都要做1software都是簡答題,主要是彙編,計算機體系結構,AMD和Intel的cpu有什麼區別,實模式與保護模式。2hardware10道簡答題1個有緣RC迴路的電流方程us=uc+dUc/dt*RC?常見的計算機總線有什麼sram,dram,sdram,ddr都是什麼串行總線,並行總線哪個更...
-
富力地產筆試題目
早上9點30到了,一開始要重新填一個公司的信息表。10點開始考試,10點半結束筆試,考的就是行測,超級簡單。複習過公務員的同學佔便宜了。題型,第一部分,富力公司的簡介,比如某年上市,某年被評為綜合實力第一等等。第二-五部分和行測一樣了,有言語理解,數列,主要是等差和等比...
-
阿里巴巴的筆試
阿里巴巴的筆試全英文寫作,狂暈1、説出一個你印象很深的人,同時寫出讓你印象深的原因2、説出從中國出口到USA的大致流程3、兩份商務回函4、公司背景翻譯5、你認為對B2B站點來説,什麼是為商業人士服務的關鍵...
相關文章
- 泰鼎(Trident) 筆試題目(IC logic design CM方向)
- Nivea(妮維雅)的Open Question
- 英語名言警句nothing is impossible to a willing mind
- Nov 9, Citi Online Test 筆經
- 豪威(Omnivision)筆試題目(2005)
- 路易威登(Louis Vuitton)面試題目
- NVIDIA公司ASIC Intern的筆試
- 英文求職信-Adminstration - Executive Assistant
- 英文簡歷(行政助理)ADMINISTRATIVE ASSISTANT(Personnel)
- 凹凸電子筆試題目(Linux Software Engineer)